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max17058/max17059 1-cell /2-cell li+ modelgauge ics simplified operating circuit general description the max17058/max17059 ics are tiny fuel gauges for lithium-ion (li+) batteries in handheld and portable equipment. the max17058 operates with a single li+ cell and the max17059 with two li+ cells in series. the ics use the sophisticated li+ battery-modeling algorithm modelgauge k to track the battery relative state-of-charge (soc) continuously over a widely varying charge/discharge conditions. the modelgauge algo - rithm eliminates current-sense resistor and battery-learn cycles required by other fuel gauges. temperature compensation is implemented using the system micro - controller. on battery insertion, the ics debounce initial voltage measurements to improve the initial soc estimate, allowing them to be located on system side. soc and voltage information is accessed using the i 2 c interface. the ics are available in a tiny 0.9mm x 1.7mm, 8-bump wafer-level package (wlp) or a 2mm x 2mm, 8-pin tdfn package. applications wireless handsets smartphones/pdas tablets and handheld computers portable game players e-readers digital still and video cameras portable medical equipment features and benefits s max17058: 1 cell, max17059: 2 cells s precision 7.5mv/cell voltage measurement s modelgauge algorithm ? provides accurate state-of-charge ? compensates for temperature/load variation ? does not accumulate errors, unlike coulomb counters ? eliminates learning ? eliminates current-sense resistor s low quiescent current: 23a s battery-insertion debounce ? best of 16 samples estimates initial soc s programmable reset for battery swap ? 2.28v to 3.48v range s low soc alert indicator s i 2 c interface ordering information appears at end of data sheet. 19-6172; rev 6; 10/14 modelgauge is a trademark of maxim integrated products, inc. evaluation kit available only one external component v dd alrt sda scl cell qstrt ctggnd system p max17058 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim?s website at www.maximintegrated.com. downloaded from: http:///
max17058/max17059 1-cell /2-cell li+ modelgauge ics 2 maxim integrated cell to gnd ......................................................... -0.3v to +12v all pins (excluding cell) to gnd .......................... -0.3v to +6v continuous sink current, sda, alrt ................................ 20ma operating temperature range .......................... -40 n c to +85 n c storage temperature range ............................ -55 n c to +125 n c lead temperature (tdfn only) (soldering, 10s) ........... +300 n c soldering temperature (reflow) ...................................... +260 n c absolute maximum ratingsstresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics (2.5v < v dd < 4.5v, -20 n c < t a < +70 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 1) electrical characteristics (i 2 c interface) (2.5v < v dd < 4.5v, -20 n c < t a < +70 n c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units supply voltage v dd (note 2) 2.5 4.5 v fuel-gauge soc reset (vreset register) v rst configuration range, in 40mv steps 2.28 3.48 v trimmed at 3v 2.85 3.0 3.15 v data i/o pins scl, sda, alrt (note 2) -0.3 +5.5 v supply current i dd0 sleep mode, t a < +50 n c 0.5 2 f a i dd1 active mode 23 40 time base accuracy t err active mode (note 3) -3.5 q 1 +3.5 % adc sample period active mode 250 ms voltage error v err v cell = 3.6v, t a = +25 n c (note 4) -7.5 +7.5 mv/cell -20 n c < t a < +70 n c -20 +20 voltage-measurement resolution 1.25 mv/cell voltage-measurement range max17058: v dd pin 2.5 5 v max17059: cell pin 5 10 sda, scl, qstrt input logic-high v ih 1.4 v sda, scl, qstrt input logic-low v il 0.5 v sda, alrt output logic-low v ol i ol = 4ma 0.4 v sda, scl bus low-detection current i pd v sda = v scl = 0.4v (note 5) 0.2 0.4 f a bus low-detection timeout t sleep (note 6) 1.75 2.5 s parameter symbol conditions min typ max units scl clock frequency f scl (note 7) 0 400 khz bus free time between a stop and start condition t buf 1.3 f s start condition (repeated) hold time t hd:sta (note 8) 0.6 f s low period of scl clock t low 1.3 f s downloaded from: http:///
max17058/max17059 1-cell /2-cell li+ modelgauge ics 3 maxim integrated note 1: specifications are tested 100% at t a = +25 n c. limits over the operating range are guaranteed by design and characterization. note 2: all voltages are referenced to gnd. note 3: test is performed on unmounted/unsoldered ports. note 4: the voltage is trimmed and verified with 16x averaging. note 5: this current is always present. note 6: the ic enters sleep mode after scl < v il and sda < v il for longer than 2.5s. note 7: timing must be fast enough to prevent the ic from entering sleep mode due to bus low for period > t sleep . note 8: f scl must meet the minimum clock low time plus the rise/fall times. note 9: the maximum t hd:dat has to be met only if the device does not stretch the low period (t low ) of the scl signal. note 10: this device internally provides a hold time of at least 100ns for the sda signal (referred to the v ih,min of the scl signal) to bridge the undefined region of the falling edge of scl. note 11: filters on sda and scl suppress noise spikes at the input buffers and delay the sampling instance. note 12: c b is total capacitance of one bus line in pf. electrical characteristics ( i 2 c interface) (continued) (2.5v < v dd < 4.5v, -20 n c < t a < +70 n c, unless otherwise noted.) (note 1) figure 1. i 2 c bus timing diagram parameter symbol conditions min typ max units high period of scl clock t high 0.6 f s setup time for a repeated start condition t su:sta 0.6 f s data hold time t hd:dat (notes 9, 10) 0 0.9 f s data setup time t su:dat (note 9) 100 ns rise time of both sda and scl signals t r 20 + 0.1c b 300 ns fall time of both sda and scl signals t f 20 + 0.1c b 300 ns setup time for stop condition t su:sto 0.6 f s spike pulse widths suppressed by input filter t sp (note 11) 0.6 50 ns capacitive load for each bus line c b (note 12) 400 pf scl, sda input capacitance c b,in 60 pf sda scl t f t low t hd:sta t hd:dat t su:sta t su:sto t su:dat t hd:sta t sp t r t buf t r t f ss r p s downloaded from: http:///
max17058/max17059 1-cell /2-cell li+ modelgauge ics 4 maxim integrated typical operating characteristics (t a = +25 n c, battery is sanyo uf504553f, unless otherwise noted.) quiescent current vs. supply voltage (active mode) max17058 toc01 v cell (v) quiescent current (a) 4.0 3.5 3.0 5 10 15 20 25 30 35 40 0 2.5 4.5 t a = +70c t a = +25c t a = -20c soc accuracy t a = 0c max17058 toc03 time (hr) soc (%) error (%) 8 6 4 reference soc modelgauge soc error 2 25 50 75 100 0 -5 0 5 10-10 01 0 soc accuracy t a = +40c max17058 toc05 time (hr) soc (%) error (%) 8 6 4 reference soc modelgauge soc error 2 25 50 75 100 0 -5 0 5 10-10 01 0 voltage adc error vs. temperature max17058 toc02 temperature (c) voltage adc error (mv/cell) 55 40 -5 10 25 -15 -10 -5 0 5 10 15 20 -20 -20 70 v cell = 3.6v v cell = 2.5v v cell = 4.5v soc accuracy t a = +20c max17058 toc04 time (hr) soc (%) error (%) 8 6 4 reference soc modelgauge error 2 25 50 75 100 0 -5 0 5 10-10 -2 01 0 downloaded from: http:///
max17058/max17059 1-cell /2-cell li+ modelgauge ics 5 maxim integrated typical operating characteristics (continued) (t a = +25 n c, battery is sanyo uf504553f, unless otherwise noted.) zigzag pattern soc accuracy (1 /3 ) max17058 toc06 time (hr) soc (%) error (%) 80 60 40 reference soc modelgauge soc error 20 25 50 75 100 0 -5 0 5 10-10 0 100 zigzag pattern soc accuracy (3 /3 ) max17058 toc08 time (hr) soc (%) error (%) reference soc modelgauge soc error 25 50 75 100 0 -5 0 5 10-10 103 101 99 97 95 105 no error accumulated after 100 hours zigzag pattern soc accuracy (2 /3 ) max17058 toc07 time (hr) soc (%) error (%) reference soc modelgauge soc error 25 50 75 100 0 -5 0 5 10-10 8 6 4 2 01 0 max17058 toc09 0a 0v 0v 0v 4ms/div debouncecompleted debouncebegins v cell ocv battery-insertion debounce/ ocv acquisition downloaded from: http:///
max17058/max17059 1-cell /2-cell li+ modelgauge ics 6 maxim integrated pin/bump configurations pin/bump description pin/bump name function tdfn wlp 1 a1 ctg connect to gnd 1 a2 cell connect to positive battery terminal.max17058: not connected internally. max17059: voltage-sense input. 3 a3 v dd power-supply input. bypass with 0.1 f f to gnd. max17058: voltage-sense input. connect to a positive battery terminal.max17059: connect to a regulated power-supply voltage. 4 a4 gnd ground. connect to a negative battery terminal. 5 b4 alrt open-drain, active-low alert output. optionally connect to the interrupt input of the system microcontroller. 6 b3 qstrt quick-start input. resets state-of-charge calculation. connect to gnd if not used. 7 b2 scl i 2 c clock input. scl has an internal pulldown (i pd ) for sensing disconnection. 8 b1 sda open-drain i 2 c data input/output. sda has an internal pulldown (i pd ) for sensing disconnection. ? ? ep exposed pad (tdfn only). connect to gnd. 1 + 34 86 5 sd aq strt alrt ep 2 7 sc l ctg v dd gnd cell tdfn top view (pad side down) a1 a2 a3 a4 b1 b2 b3 b4 + top view (bump side down) max17058max17059 wlp ct gc el lv dd gnd sda scl qstrt alrt max17058max17059 downloaded from: http:///
max17058/max17059 1-cell /2-cell li+ modelgauge ics 7 maxim integrated detailed description modelgauge theory of operation the max17058/max17059 ics simulate the internal, non - linear dynamics of a li+ battery to determine its state of charge (soc). the sophisticated battery model consid - ers impedance and the slow rate of chemical reactions in the battery ( figure 2 ). the modelgauge algorithm performs best with a custom model, obtained by characterizing the battery at multiple discharge currents and temperatures to precisely model it. contact maxim if you need a custom model. at power- on reset (por), the ics have a preloaded rom model that performs well for some batteries. fuel-gauge performance in coulomb counter-based fuel gauges, soc drifts because offset error in the current-sense adc measure - ment accumulates over time. instantaneous error can be very small, but never precisely zero. error accumulates over time in such systems (typically 0.5%?2% per day) and requires periodic corrections. some algorithms cor - rect drift using occasional events, and until such an event occurs the algorithm?s error is boundless: reaching predefined soc levels near full or empty measuring the relaxed battery voltage after a long period of inactivity completing a full charge/discharge cycle the modelgauge algorithm requires no correction events because it uses only voltage, which is stable over time. as the soc accuracy without full/empty/relax shows the algorithm remains accurate despite the absence of any of the above events; it neither drifts nor accumulates error over time. to correctly measure performance of a fuel gauge as experienced by end-users, exercise the battery dynami - cally; accuracy cannot be fully determined from only simple cycles. battery voltage and state-of-charge the open-circuit voltage (ocv) of a li+ battery uniquely determines its soc; one soc can have only one value of ocv. in contrast, a given v cell can occur at many dif - ferent values of ocv because v cell is a function of time, ocv, load, temperature, age, and impedance, etc.; one value of ocv can have many values of v cell . therefore, one soc can have many values of v cell , so v cell can - not uniquely determine soc. figure 3 shows that v cell = 3.81v occurs at 2%, 50%, and 72% soc.even the use of sophisticated tables to consider both voltage and load results in significant error due to the load transients typically experienced in a system. during charging or discharging, and for approximately 30min after, v cell and ocv differ substantially, and v cell has been affected by the preceding hours of battery activity. modelgauge uses voltage comprehensively by using voltage measured over a long period of time. figure 2. block diagram figure 3. instantaneous voltage does not translate directly to soc state machine (soc) i 2 c interface ic ground time base (32khz) adc (v cell ) voltage reference bias gnd cell v dd scl sda alrt qstrt max17058max17059 time (hr) soc v cell 100% 80%60% 40% 20% 0% 012345678 3.4v 3.6v 3.8v 4.0v 4.2v3.2v 3.81v = 2% 3.81v = 72% 3.81v = 50% 3.81v v cell soc downloaded from: http:///
max17058/max17059 1-cell /2-cell li+ modelgauge ics 8 maxim integrated temperature compensation for best performance, the host microcontroller must measure battery temperature periodically, and compensate the rcomp modelgauge parameter accordingly, at least once per minute. each custom model defines constants rcomp0 (default is 0x97), tempcoup (default is -0.5), and tempcodown (default is -5.0). to calculate the new value of config.rcomp: // t is battery temperature (degrees celsius)if (t > 20) { rcomp = rcomp0 + (t - 20) x tempcoup; } else { rcomp = rcmop0 + (t - 20) x tempcodown; } impact of empty-voltage selection most applications have a minimum operating voltage below which the system immediately powers off (empty voltage). when characterizing the battery to create a cus - tom model, choose empty voltage carefully. as shown in figure 4 , capacity unavailable to the system increases at an accelerating rate as empty voltage increases.to ensure a controlled shutdown, consider including operating margin into the fuel gauge based on some low threshold of soc, for example, shutting down at 3% or 5%. this utilizes the battery more effectively than adding error margin to empty voltage. battery insertion when the battery is first inserted into the system, the fuel-gauge ic has no previous knowledge about the battery?s soc. assuming that the battery is relaxed, the ic translates its first v cell measurement into the best initial estimate of soc. initial error caused by the battery not being in a relaxed state diminishes over time, regard - less of loading following this initial conversion. while the soc estimated by the coulomb counter diverges, the modelgauge soc converges, correcting error automati - cally as illustrated in figure 5 ; initial error has no long- lasting impact. battery-insertion debounce any time the ic powers on or resets (see the vreset register (0x18) section), it estimates that ocv is the maximum of 16 v cell samples (1ms each, full 12-bit resolution). ocv is ready 17ms after battery insertion, and soc is ready 175ms after that. figure 4. increasing empty voltage reduces battery capacityfigure 5. modelgauge heals error automatically target empty voltage (v) capacity lost (%) 6050 40 30 20 10 0 3.0 3.1 3.2 3.3 3.4 3.5 c/3 load c/10 load longer battery relaxation improves initial accuracy relaxation time before insertion (minutes) initial voltage error (mv) soc error (%) 0mv -10mv-20mv 0%-5% -10% 0.1 11 0 100 1000 soc error voltage erro r modelgauge heals error automatically over time time after insertion (minutes) socsoc 0% -5% -10% 30% 45%15% 0% 02 04 06 08 0 relaxed soc reference soc relaxed error unrelaxed error unrelaxed soc downloaded from: http:///
max17058/max17059 1-cell /2-cell li+ modelgauge ics 9 maxim integrated battery-swap detection if v cell falls below v rst then returns above v rst , the ic quick-starts. this handles the battery swap; the soc of the previous battery doesn not affect that of the new one. see the quick-start and vreset register (0x18) sections. quick-start if the ic generates an erroneous initial soc, the bat - tery insertion and system power-up waveforms must be examined to determine if a quick-start is necessary, as well as the best time to execute the command. the ic samples the maximum v cell during the first 17ms (see the battery insertion section). unless v cell is fully relaxed, even the best sampled voltage can appear greater or less than ocv. therefore, quick-start must be used cautiously. most systems should not use quick-start because the ics handle most startup problems transparently, such as intermittent battery-terminal connection during inser - tion. if battery voltage stabilizes faster than 17ms, as illustrated in figure 6 , then do not use quick-start. the quick-start command restarts fuel-gauge calcula - tions in the same manner as initial power-up of the ic. if the system power-up sequence is so noisy that the initial estimate of soc has unacceptable error, the system microcontroller might be able to reduce the error by using quick-start. a quick-start is initiated by a rising edge on the qstrt pin, or by writing 1 to the quick-start bit on the mode register. figure 7 illustrates a waveform that could corrupt the initial soc. if the disturbance is severe, quick-start after the inrush current has stopped and voltage has settled, but before the system is fully powered. if issued too soon or too late, a quick-start causes soc error. large inrush current might reduce v cell longer than the initial sampling period. issue a quick-start so that v cell is nearest ocv during the 17ms following the command.if the ic remains powered by a charger when the cell is removed, then it continues to measure the charge volt - age even though the cell is not present. when the cell is reinserted, quick-start before the charger affects v cell . power-on reset (por) por includes a quick-start, so only use it for when a quick-start is safe (see the quick-start section). this command restores all registers to their default values. after this command, reload the custom model. see the cmd register (0xfe) section. alert interrupt the ics can interrupt a system microcontroller when soc becomes low. see the config register (0x0c) and status register (0x1a) sections. when the alert is triggered, the ic asserts the alrt pin logic-low and sets config.alrt = 1. the alrt pin remains logic-low until the system writes config.alrt = 0 to clear the alert. the alert function is enabled by default and can occur immediately upon power-up. entering sleep mode does not clear the alrt bit or the alrt pin. figure 6. insertion waveform not requiring quick-start command figure 7. insertion waveform requiring quick-start command steady systemload begins v cell has fully relaxed time 17ms v cell initial sample debounce window time 17ms v cell initial sample debounce window quick-start during this time span steady systemload begins best time to quick-start v ce ll has fully relaxed downloaded from: http:///
max17058/max17059 1-cell /2-cell li+ modelgauge ics 10 maxim integrated sleep mode in sleep mode, the ic halts all operations, reducing current consumption (below 1 f a). after exiting sleep mode, the ic continues normal operation. in sleep mode, the ic does not detect self-discharge. if the battery changes state while the ic sleeps, the ic cannot detect it, causing soc error. wake up the ic before charging or discharging. to enter sleep mode, either: hold sda and scl logic-low for a period of t sleep . a rising edge on sda or scl wakes up the ic. write config.sleep = 1. to wake up the ic, write config.sleep = 0. other communication does not wake up the ic. por wakes up the ic. register summary all registers must be written and read as 16-bit words; 8-bit writes cause no effect. any bits marked x (don?t care) or read only must be written with the rest of the register, but the value written is ignored by the ic. the values read from don?t care bits are undefined. calculate the register?s value by multiplying the 16-bit word by the register?s lsb value, as shown in table 1 . vcell register (0x02) the max17058 measures vcell between the v dd and gnd pins. the max17059 measures vcell between the cell and gnd pins. the register value is the average of four adc conversions. the value updates every 250ms in active mode. soc register (0x04) the modelgauge algorithm calculates relative soc, automatically adapting to variation in battery size. the upper byte least-significant bit has units of 1%. the first update is available approximately 1s after por. subsequent updates occur at variable intervals depending on application conditions. mode register (0x06) the mode register allows the system processor to send special commands to the ic (see figure 8 ). quick-start estimates soc assuming ocv is equal to immediate v cell . use with caution; see the quick- start section. table 1. register summaryfigure 8. mode register format address register name 16-bit lsb description read/write default 0x02 vcell 78.125 f v/cell adc measurement of v cell . r ? 0x04 soc 1%/256 battery state of charge. r ? 0x06 mode ? initiates quick-start and enables sleep mode. w 0x0000 0x08 version ? ic production version. r 0x001_ 0x0c config ? compensation to optimize performance, sleep mode, alert indicators, and configuration. r/w 0x971c 0x18 vreset ? configures vcell threshold below which the ic resets itself. r/w 0x96__ 0x1a status ? low soc alert and reset indicators. r/w 0x01__ 0x40 to 0x7f table ? configures the battery parameters. w ? 0xfe cmd ? sends por command. r/w 0xffff msb?address 0x06 lsb?address 0x07 x quick- start x x x x x x x x x x x x x x msb lsb msb lsb downloaded from: http:///
max17058/max17059 1-cell /2-cell li+ modelgauge ics 11 maxim integrated version register (0x08) the value of this read-only register indicates the production version of the ic (0x0011). config register (0x0c) see figure 9 . rcomp compensates the model for different lithium chemistries. the system must adjust rcomp periodi - cally (see the temperature compensation section). the por value of rcomp is 0x97. sleep forces the ic in or out of sleep mode. writing 1 forces the ic to enter sleep mode, and 0 forces the ic to exit. the por value of sleep is 0. use with caution (see the sleep mode section). alrt (alert status bit) is set by the ic when soc becomes low. when this bit is set, the alrt pin asserts low. clear to deassert the alrt pin. the por value is 0 (see the alert interrupt section). athd (empty alert threshold) sets the soc threshold, where an interrupt is generated on the alrt pin and can be programmed from 1% up to 32%. the value is (32 - athd)% (e.g., 00000b 32% 00001b 31%, 00010b 30%, 11111b 1%). the por value of athd is 0x1c or 4%. the alert occurs only on a falling edge past this threshold. vreset register (0x18) see figure 10 . vreset[7:1] adjusts a fast analog comparator and a slower digital adc threshold to detect battery removal and reinsertion. for captive batteries, set to 2.5v. for removable batteries, set to at least 300mv below the application?s empty voltage according to the desired reset threshold for your application. if the comparator is enabled, the ic resets 1ms after v cell rises above the threshold. otherwise, the ic resets 250ms after the vcell register rises above the threshold. status register (0x1a) see figure 11 . u ri (reset indicator) is set when the device powers up. any time this bit is set, the ic is not configured, so the custom model and any other configuration must be immediately reloaded and the bit should be cleared. figure 9. config register formatfigure 10. vreset register format figure 11. status register format msb?address 0x1a lsb?address 0x1b x x x hd x x x ri x x x x x x x x msb lsb msb lsb msb (rcomp)?address 0x0c lsb?address 0x0d rcomp 7 rcomp 6 rcomp 5 rcomp 4 rcomp 3 rcomp 2 rcomp 1 rcomp 0 sleep x alrt athd msb lsb msb lsb msb (vreset)?address 0x18 lsb (id)?address 0x19 2 6 2 5 2 4 2 3 2 2 2 1 2 0 dis id 7 id 6 id 5 id 4 id 3 id 2 id 1 id 0 msb lsb msb lsb vreset 2 0 units: 40mv downloaded from: http:///
max17058/max17059 1-cell /2-cell li+ modelgauge ics 12 maxim integrated table registers (0x40 to 0x7f) contact maxim for details on how to configure these registers. the default value is appropriate for some li+ batteries.to unlock the table registers, write 0x57 to address 0x3f, and 0x4a to address 0x3e. while the table is unlocked, no modelgauge registers are updated, so relock as soon as possible by writing 0x00 to address 0x3f, and 0x00 to address 0x3e. cmd register (0xfe) writing a value of 0x5400 to this register causes the device to completely reset as if power had been removed. use with caution (see the power-on reset (por) section). the reset occurs when the last bit has been clocked in. the ic does not respond with an i 2 c ack after this command sequence. application examples the ics have a variety of configurations, depending on the application. table 2 shows the most common system configurations and the proper pin connections for each.in all cases, the system must provide pullup circuits for alrt (if used), sda, and scl. figure 12 shows an example application for a 1s cell pack. in this example, the alrt pin is connected to the microcontroller?s interrupt input so the max17058 indicates when the battery becomes low. the qstrt pin is unused in this application and is connected to gnd. figure 13 shows a max17059 example application using a 2s cell pack. the max17059 is mounted on the sys - tem side and powered from a 3.3v supply generated by the system. the cell pin is still connected directly to pack+. table 2. possible application configurations figure 12. max17058 application circuit (1s cell pack) figure 13. max17059 application circuit (2s cell pack) system configuration ic v dd alrt qstrt 1s pack-side location max17058 power directly from battery leave unconnected connect to gnd 1s host-side location max17058 power directly from battery leave unconnected connect to gnd 1s host-side location, low-cell interrupt max17058 power directly from battery connect to system interrupt connect to gnd 1s host-side location, hardware quick-start max17058 power directly from battery leave unconnected connect to rising-edge reset signal 2s pack-side location max17059 power from +2.5v to +4.5v ldo in pack leave unconnected connect to gnd 2s host-side location max17059 power from +2.5v to +4.5v ldo or pmic leave unconnected connect to gnd 2s host-side location, low-cell interrupt max17059 power from +2.5v to +4.5v ldo or pmic connect to system interrupt connect to gnd 2s host-side location, hardware quick-start max17059 power from +2.5v to +4.5v ldo or pmic leave unconnected connect to rising-edge reset signal v dd alrt sda scl cell qstrt ctggnd interrupti 2 c bus master system p max17058 battery pack protection 0.1f note: system required to provide pullup circuits for alrt, sda, and scl. v dd alrt sda scl cell qstrt ctggnd max17059 battery pack protection 0.1f 2.5v to 4.5v output from system interrupti 2 c bus master system p note: system required to provide pullup circuits for alrt, sda, and scl. downloaded from: http:///
max17058/max17059 1-cell /2-cell li+ modelgauge ics 13 maxim integrated i 2 c bus system the i 2 c bus system supports operation as a slave-only device in a single or multislave, and single or multimaster system. slave devices can share the bus by uniquely setting the 7-bit slave address. the i 2 c interface con - sists of a serial-data line (sda) and serialclock line (scl). sda and scl provide bidirectional communica - tion between the ics slave device and a master device at speeds up to 400khz. the ics? sda pin operates bidirectionally; that is, when the ics receive data, sda operates as an input, and when the ics return data, sda operates as an open-drain output, with the host system providing a resistive pullup. the ics always operate as a slave device, receiving and transmitting data under the control of a master device. the master initiates all transactions on the bus and generates the scl signal, as well as the start and stop bits, which begin and end each transaction. bit transfer one data bit is transferred during each scl clock cycle, with the cycle defined by scl transitioning low-to-high and then high-to-low. the sda logic level must remain stable during the high period of the scl clock pulse. any change in sda when scl is high is interpreted as a start or stop control signal. bus idle the bus is defined to be idle, or not busy, when no master device has control. both sda and scl remain high when the bus is idle. the stop condition is the proper method to return the bus to the idle state. start and stop conditions the master initiates transactions with a start condition (s) by forcing a high-to-low transition on sda while scl is high. the master terminates a transaction with a stop condition (p), a low-to-high transition on sda while scl is high. a repeated start condition (sr) can be used in place of a stop then start sequence to terminate one transaction and begin another without returning the bus to the idle state. in multimaster systems, a repeated start allows the master to retain control of the bus. the start and stop conditions are the only bus activities in which the sda transitions when scl is high. acknowledge bits each byte of a data transfer is acknowledged with an acknowledge bit (a) or a no-acknowledge bit (n). both the master and the max17058/max17059 slave generate acknowledge bits. to generate an acknowl - edge, the receiving device must pull sda low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low until scl returns low. to gener - ate a no-acknowledge (also called nak), the receiver releases sda before the rising edge of the acknowledge- related clock pulse and leaves sda high until scl returns low. monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsuccessful data transfer can occur if a receiving device is busy or if a system fault has occurred. in the event of an unsuc - cessful data transfer, the bus master should reattempt communication. data order a byte of data consists of 8 bits ordered most significant bit (msb) first. the least significant bit (lsb) of each byte is followed by the acknowledge bit. the ic registers composed of multibyte values are ordered msb first. the msb of multibyte registers is stored on even data- memory addresses. slave address a bus master initiates communication with a slave device by issuing a start condition followed by a slave address (saddr) and the read/write (r/w) bit. when the bus is idle, the ics continuously monitor for a start condition followed by its slave address. when the ics receive a slave address that matches the value in the slave address register, they respond with an acknowledge bit during the clock period following the r/w bit. the 7-bit slave address is fixed to 6ch (write)/6dh (read): read/write bit the r/w bit following the slave address determines the data direction of subsequent bytes in the transfer. r/w = 0 selects a write transaction with the following bytes being written by the master to the slave. r/w = 1 selects a read transaction with the following bytes being read from the slave by the master ( table 3 ). 0 110110 max 17058 /m ax17059 sla ve addre ss downloaded from: http:///
max17058/max17059 1-cell /2-cell li+ modelgauge ics 14 maxim integrated bus timing the ics are compatible with any bus timing up to 400khz. no special configuration is required to operate at any speed. i 2 c command protocols the command protocols involve several transaction formats. the simplest format consists of the master writing the start bit, slave address, r/w bit, and then monitoring the acknowledge bit for presence of the ics. more complex formats, such as the write data and read data, read data and execute device-specific operations. all bytes in each command format require the slave or host to return an acknowledge bit before continuing with the next byte. table 3 shows the key that applies to the transaction formats. basic transaction formats a write transaction transfers 2 or more data bytes to the ics. the data transfer begins at the memory address supplied in the maddr byte. control of the sda signal is retained by the master throughout the transaction, except for the acknowledge cycles: a read transaction transfers 2 or more bytes from the ics. read transactions are composed of two parts, a write portion followed by a read portion, and are therefore inherently longer than a write transaction. the write portion communicates the starting point for the read operation. the read portion follows immediately, beginning with a repeated start, slave address with r/w set to a 1. control of sda is assumed by the ics, beginning with the slave address acknowledge cycle. control of the sda signal is retained by the ics through - out the transaction, except for the acknowledge cycles. the master indicates the end of a read transaction by responding to the last byte it requires with a no acknowl - edge. this signals the ics that control of sda is to remain with the master following the acknowledge clock. write data protocol the write data protocol is used to write to register to the ics starting at memory address maddr. data0 represents the data written to maddr, data1 represents the data written to maddr + 1, and datan represents the last data byte, written to maddr + n. the master indicates the end of a write transaction by sending a stop or repeated start after receiving the last acknowledge bit: the msb of the data to be stored at address maddr can be written immediately after the maddr byte is acknowledged. because the address is automatically incremented after the lsb of each byte is received by the ics, the msb of the data at address maddr + 1 can be written immediately after the acknowledgment of the data at address maddr. if the bus master continues an autoincremented write transaction beyond address 4fh, the ics ignore the data. a valid write must include both register bytes. data is also ignored on writes to read- only addresses. incomplete bytes and bytes that are not acknowledged by the ics are not written to memory. table 3. i 2 c protocol key read: s. saddr w. a. maddr. a. sr. saddr r. a. data0. a. data1. n. p write portion read portion write: s. saddr w. a. maddr. a. data0. a. data1. a. p s. saddr w. a. maddr. a. data0. a. data1. a... datan. a. p key description key description s start bit sr repeated start saddr slave address (7 bit) w r/w bit = 0 maddr memory address byte p stop bit data data byte written by master data data byte returned by slave a acknowledge bit?master a acknowledge bit?slave n no acknowledge?master n no acknowledge bit?slave downloaded from: http:///
max17058/max17059 1-cell /2-cell li+ modelgauge ics 15 maxim integrated read data protocol the read data protocol is used to read to register from the ics starting at the memory address specified by maddr. both register bytes must be read in the same transaction for the register data to be valid. data0 represents the data byte in memory location maddr, data1 represents the data from maddr + 1, and datan represents the last byte read by the master: data is returned beginning with the msb of the data in maddr. because the address is automatically incre - mented after the lsb of each byte is returned, the msb of the data at address maddr + 1 is available to the host immediately after the acknowledgment of the data at address maddr. if the bus master continues to read beyond address ffh, the ics output data values of ffh. addresses labeled reserved in the memory map return undefined data. the bus master terminates the read transaction at any byte boundary by issuing a no acknowledge followed by a stop or repeated start. package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. ordering information + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. t = tape and reel. package type package code outline no. land pattern no. 8 wlp w80b1+1 21-0555 refer to application note 1891 8 tdfn-ep t822+3 21-0168 90-0065 part temp range pin-package description max17058 g+ -40 n c to +85 n c 8 tdfn-ep* 1-cell modelgauge ic max17058g+t10 -40 n c to +85 n c 8 tdfn-ep* 1-cell modelgauge ic max17058x+ -40 n c to +85 n c 8 wlp 1-cell modelgauge ic max17058x+t10 -40 n c to +85 n c 8 wlp 1-cell modelgauge ic max17059 g+ -40 n c to +85 n c 8 tdfn-ep* 2-cell modelgauge ic max17059g+t10 -40 n c to +85 n c 8 tdfn-ep* 2-cell modelgauge ic max17059x+ -40 n c to +85 n c 8 wlp 2-cell modelgauge ic max17059x+t10 -40 n c to +85 n c 8 wlp 2-cell modelgauge ic s. saddr w. a. maddr. a. sr. saddr r. a. data0. a. data1. a... datan. n. p downloaded from: http:///
max17058/max17059 1-cell /2-cell li+ modelgauge ics maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 16 ? 2014 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 2/12 initial release ? 1 4/12 corrected byte-order errors 10, 11 2 6/12 updated absolute maximum ratings section; corrected memory address for cmd 2, 9, 12 3 8/12 corrected formula for rcomp and tempco 8 4 6/13 corrected conditions for entering sleep mode and absolute maximum voltage ratings, and removed all mentions of ensleep 2, 10 5 8/13 corrected the device version number 10 6 10/14 updated vreset recommendation from 40mv?80mv to 300mv below empty voltage 11 downloaded from: http:///

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